Storage device, computing system including the storage device, and method of operating the storage device

ABSTRACT

A storage device includes a storage medium and a controller configured to control the storage medium. The controller includes an interface unit configured to interface with a host, a processing unit connected to the interface unit via a first signal line and configured to process a direct load operation and a direct store operation between the host and the controller, and at least one memory connected to the interface unit via a second signal line. The at least one memory is configured to temporarily store data read from the storage medium or data received from the host, and is configured to be directly accessed by the host.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/613,462 filed Feb. 4, 2015, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0052972, filed on Apr. 30,2014, the disclosures of which are incorporated by reference herein intheir entireties.

TECHNICAL FIELD

Exemplary embodiments of the present inventive concept relate to astorage device, and more particularly, to a storage device, a computingsystem including the storage device, and a method of operating thestorage device.

DISCUSSION OF THE RELATED ART

Recently, a solid state drive (SSD) using a nonvolatile memory devicehas been developed as a next generation storage device used in place ofa hard disk drive (HDD). An SSD replaces a mechanical configuration ofan HDD with a nonvolatile memory device, resulting in a high operatingspeed and stability while occupying a smaller amount of space.

SUMMARY

According to an exemplary embodiment of the present inventive concept astorage device includes a storage medium and a controller configured tocontrol the storage medium. The controller includes an interface unitinterfacing with a host, a processing unit connected to the interfaceunit via a first signal line and configured to process a direct loadoperation or a direct store operation between the host and thecontroller, and at least one memory connected to the interface unit viaa second signal line. The at least one memory temporarily stores dataread from the storage medium or data received from the host and isdirectly accessible by the host.

The interface unit may be a first interface unit interfacing with thehost according to a first standardized interface, and the controller mayfurther include a second interface unit interfacing with the firstinterface unit according to a second standardized interface.

The first signal line may directly connect the first interface unit andthe processing unit to each other, not via the second interface unit,and the second signal line may directly connect the first interface unitand the at least one memory to each other, not via the second interfaceunit.

The first standardized interface may be a peripheral componentinterconnect express (PCIe) and the second standardized interface may bea nonvolatile memory express (NVMe) or a small computer system interfaceexpress (SCSIe).

The processing unit may include at least one processor configured toprocess the direct load operation or the direct store operation, and atleast one tightly coupled memory (TCM) disposed adjacent to the at leastone processor and accessible by the at least one processor within arelatively short time period.

The at least one TCM may temporarily store a data transfer commandbetween the controller and the storage medium.

The data transfer command may include a flush command for transferringdata temporarily stored in the at least one memory to the storage mediumand a fill command for transferring the data stored in the storagemedium to the at least one memory.

The at least one TCM may include at least one special function register(SFR) used to perform the direct load operation or the direct storeoperation.

The at least one memory may include at least one of a first memorytemporarily storing raw data read from the storage medium or raw datareceived from the host, and a second memory temporarily storing metadatarelating to the raw data.

The at least one of the first memory and the second memory may includeat least one SFR used to perform the direct load operation or the directstore operation.

The interface unit may include a signal transfer unit configured totransmit and receive a signal to and from the host, and an addressconversion unit configured to perform an address conversion between anexternal address of the signal and an internal address suitable forinternal communication within the controller.

The controller may include a first bus connected to the interface unit,a second bus connected to the processing unit, and a third bus connectedto the at least one memory. The first signal line may be directlyconnected between the first bus and the second bus, and the secondsignal line may be directly connected between the first bus and thethird bus.

According to an exemplary embodiment of the present inventive concept, acomputing system includes a storage device including a storage mediumand a controller configured to control the storage medium and includingat least one memory, and a host configured to directly access the atleast one memory with reference to an address map having an addressspace corresponding to the at least one memory.

The host may include a processor and a main memory connected to theprocessor. The processor may directly access the at least one memory,not via the main memory.

The controller may further include an interface unit interfacing withthe host, and a processing unit connected to the interface unit via afirst signal line and configured to process a direct load operation anda direct store operation between the host and the controller. The atleast one memory may be connected to the interface unit via a secondsignal line, and may temporarily store data read from the storage mediumor data received from the host.

The processing unit may include at least one processor configured toprocess the direct load operation or the direct store operation, and atleast one tightly coupled memory (TCM) disposed adjacent to the at leastone processor and accessible by the at least one processor within arelatively short time period.

The at least one memory and the at least one TCM may be respectivelymapped to address spaces that are exclusive from each other in theaddress map.

The host may include a plurality of base address registers (BARs)storing the address map. At least one BAR from the plurality of BARs maystore address spaces that are exclusive from each other and used toperform the direct load operation and the direct store operation withrespect to the at least one memory.

According to an exemplary embodiment of the present inventive concept, amethod of operating a storage device including a storage medium and acontroller for controlling the storage medium and including at least onememory includes receiving a direct load command instructing a directload operation to be executed or a direct store command instructing adirect store operation to be executed from a host, and determining astate of the at least one memory for performing the direct loadoperation or the direct store operation. The at least one memory may bedirectly accessed by the host, and the direct load operation or thedirect store operation may be performed between the host and the atleast one memory by loading data temporarily stored in the at least onememory to the host or temporarily storing data received from the host inthe at least one memory based on a result of the determining.

The determining of the state of the at least one memory may include,when the direct load command is received from the host, determiningwhether there is first data corresponding to the direct load command inthe at least one memory, and when the direct store command is receivedfrom the host, determining whether there is available space for storingsecond data corresponding to the direct store command in the at leastone memory.

The performing of the direct load operation or the direct storeoperation may include, if the first data is not stored in the at leastone memory, performing a fill operation for transmitting the first datafrom the storage medium to the at least one memory, and when the filloperation is finished, loading the first data to the host.

The performing of the direct load operation or the direct storeoperation may include, if there is no available space in the at leastone memory, performing a flush operation for transmitting datatemporarily stored in the at least one memory to the storage medium, andwhen the flush operation is finished, temporarily storing the seconddata in the at least one memory.

The method may further include, before receiving the direct load commandor the direct store command, storing device information relating to thestorage device in the at least one memory so that the host may recognizethe device information for performing the direct load operation or thedirect store operation.

The storing of the device information in the at least one memory mayinclude loading the device information in the at least one memory fromthe storage medium according to an operation initiation signal or aninitialization command, and writing the device information in the atleast one memory by the host.

The controller may include at least one processor, and at least onetightly coupled memory (TCM) disposed adjacent to the at least oneprocessor and accessible by the at least one processor within arelatively short time period. The at least one memory and the at leastone TCM are respectively mapped to address spaces that are exclusivefrom each other in the address map.

According to an exemplary embodiment of the present inventive concept, acomputing system includes a storage device including a storage mediumand a controller configured to control the storage medium. Thecontroller includes a processing unit and at least one memory. Thecomputing system further includes a host including a processor and amain memory connected to the processor. The processor is configured todirectly access the at least one memory without accessing the mainmemory.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present inventive concept willbecome more apparent by describing in detail exemplary embodimentsthereof with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a computing system according to anexemplary embodiment of the present inventive concept.

FIG. 2 is a block diagram of an example of the controller included in astorage device shown in FIG. 1 according to an exemplary embodiment ofthe present inventive concept.

FIG. 3 is a block diagram of an example of the controller included inthe storage device shown in FIG. 1 according to an exemplary embodimentof the present inventive concept.

FIG. 4 is a block diagram of an example of a processing unit included inthe controller of FIG. 2 according to an exemplary embodiment of thepresent inventive concept.

FIG. 5 is a block diagram of an example of the processing unit includedin the controller of FIG. 2 according to an exemplary embodiment of thepresent inventive concept.

FIG. 6 is a block diagram of an example of the processing unit includedin the controller of FIG. 2 according to an exemplary embodiment of thepresent inventive concept.

FIG. 7 is a block diagram of at least one memory included in thecontroller of FIG. 2 according to an exemplary embodiment of the presentinventive concept.

FIG. 8 is a block diagram of an example of the at least one memoryincluded in the controller of FIG. 2 according to an exemplaryembodiment of the present inventive concept.

FIG. 9 is a block diagram of a special function register (SFR) includedin the processing unit of FIG. 5 or the memory of FIG. 8 according toexemplary embodiments of the present inventive concept.

FIG. 10 is a block diagram of a computing system according to anexemplary embodiment of the present inventive concept.

FIG. 11 is a diagram showing an example of an address map of memoriesincluded in a controller of FIG. 10 according to an exemplary embodimentof the present inventive concept.

FIG. 12 is a block diagram of a computing system according to anexemplary embodiment of the present inventive concept.

FIG. 13 is a diagram showing an example of an address map of memoriesincluded in a controller of FIG. 12 according to an exemplary embodimentof the present inventive concept.

FIG. 14 is a block diagram of a computing system according to anexemplary embodiment of the present inventive concept.

FIG. 15 is a diagram showing an example of an address map of memoriesincluded in a controller of FIG. 14 according to an exemplary embodimentof the present inventive concept.

FIG. 16 is a diagram showing an example of an address map used in thecomputing system of FIG. 1 according to an exemplary embodiment of thepresent inventive concept.

FIG. 17 is a diagram of at least one memory included in the controllerof FIG. 2 according to an exemplary embodiment of the present inventiveconcept.

FIG. 18 is a block diagram of an interface unit included in thecontroller of FIG. 2 according to an exemplary embodiment of the presentinventive concept.

FIG. 19 is a block diagram of an example of the interface unit includedin the controller of FIG. 2 according to an exemplary embodiment of thepresent inventive concept.

FIG. 20 is a diagram illustrating an operation of an address conversionunit included in the interface unit of FIG. 18 according to an exemplaryembodiment of the present inventive concept.

FIG. 21 is a block diagram of a second interface unit included in thecontroller of FIG. 3 according to an exemplary embodiment of the presentinventive concept.

FIG. 22 is a flowchart illustrating a method of operating a storagedevice according to an exemplary embodiment of the present inventiveconcept.

FIG. 23 is a flowchart illustrating a method of operating a storagedevice according to an exemplary embodiment of the present inventiveconcept.

FIG. 24 is a schematic diagram illustrating an example of operation S110of FIG. 23 according to an exemplary embodiment of the present inventiveconcept.

FIG. 25 is a schematic diagram illustrating an example of operation S110of FIG. 23 according to an exemplary embodiment of the present inventiveconcept.

FIG. 26 is a flowchart illustrating a method of operating a storagedevice according to an exemplary embodiment of the present inventiveconcept.

FIG. 27 is a schematic diagram showing a direct load operation accordingto an exemplary embodiment of the present inventive concept.

FIG. 28 is a schematic diagram showing a direct load operation accordingto an exemplary embodiment of the present inventive concept.

FIG. 29 is a diagram showing an example of a fill operation shown inFIG. 28 according to an exemplary embodiment of the present inventiveconcept.

FIG. 30 is a diagram showing an example of an operation of setting afill operation bitmap shown in FIG. 29 according to an exemplaryembodiment of the present inventive concept.

FIG. 31 is a schematic diagram of a direct store operation according toan exemplary embodiment of the present inventive concept.

FIG. 32 is a schematic diagram of a direct store operation according toan exemplary embodiment of the present inventive concept.

FIG. 33 is a diagram showing an example of a flush operation shown inFIG. 32 according to an exemplary embodiment of the present inventiveconcept.

FIG. 34 is a diagram showing an example of an operation of setting apage index to be flushed, as shown in FIG. 33, according to an exemplaryembodiment of the present inventive concept.

FIG. 35 is a block diagram of a memory system according to an exemplaryembodiment of the present inventive concept.

FIG. 36 is a block diagram of a storage system according to an exemplaryembodiment of the present inventive concept.

FIG. 37 is a block diagram of a user device according to an exemplaryembodiment of the present inventive concept.

FIG. 38 is a block diagram of a storage server according to an exemplaryembodiment of the present inventive concept.

FIG. 39 is a block diagram of a storage server according to an exemplaryembodiment of the present inventive concept.

FIGS. 40 through 42 are schematic diagrams of systems in which thestorage devices according to one or more exemplary embodiments of thepresent inventive concept are provided.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present inventive concept will be describedmore fully hereinafter with reference to the accompanying drawings. Likereference numerals may refer to like elements throughout theaccompanying drawings.

While such terms as “first,” “second,” etc., may be used to describevarious components, such components are not limited by these terms. Theabove terms are used only to distinguish one component from another. Forexample, a first element may be designated as a second element, andsimilarly, a second element may be designated as a first element withoutdeparting from the teachings of the present inventive concept.

FIG. 1 is a block diagram of a computing system 1 according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 1, the computing system 1 may include a storage device10 and a host 20. The host 20 may include a processor 21 and a mainmemory 22. In addition, the storage device 10 may include a controller100 and a storage medium 200. The controller 100 may include aprocessing unit 110 and at least one memory 120.

The host 20 may be, for example, a user device such as apersonal/portable computer (e.g., a desktop computer, a laptop computer,a smartphone, a tablet computer, etc.), a personal digital assistant(PDA), a portable multimedia player (PMP), an MP3 player, etc.

The storage medium 200 may be, for example, a nonvolatile memory devicehaving a large storage capacity. In an exemplary embodiment, the storagemedium 200 may include a plurality of nonvolatile memory devices. Inthis case, each of the nonvolatile memory devices may be connected tothe controller 100 by a channel unit.

In exemplary embodiments of the present inventive concept, the storagemedium 200 may include a NAND-type flash memory. The NAND-type flashmemory may be, for example, a three-dimensional (3D) vertical NAND-typeflash memory or a NAND-type flash memory having a two-dimensional (2D)horizontal structure. However, the storage medium 200 is not limitedthereto. For example, the storage medium 200 may be a resistive memorysuch as a resistive random access memory (RRAM), a phase change RAM(PRAM), or a magnetic RAM (MRAM).

The computing system 1 may perform various computing operationsaccording to a load command and a store command. For example, in anexemplary embodiment, the load command may instruct the computing system1 to read data from the memory 120 and store the data in a certainregister in the processor 21, and the store command may instruct thecomputing system 1 to record a value included in a certain register ofthe processor 21 in the memory 120.

According to a normal load/store (NLS) operation, the processor 21 mayaccess the main memory 22 in the host 20. For example, in the normalload operation, the processor 21 loads data from the main memory 22, andin the normal store operation, the processor 21 may temporarily storethe data in the main memory 22. The NLS operation may be performed by,for example, a memory management unit included in the host 20.

According to a normal read operation (NRD) and a normal write operation(NWR), using the NLS operation, the data may be transmitted between theprocessor 21 and the main memory 22 and between the main memory 22 andthe storage device 10. The data transfer between the main memory 22 andthe storage device 10 may be performed by the controller 100.

Referring to the NRD operation, the data is transferred from the storagedevice 10 to the main memory 22 and temporarily stored in the mainmemory 22, and the data temporarily stored in the main memory 22 maythen be transferred to the processor 21. Referring to the NWR operation,the data is temporarily stored in the main memory 22 first, and the datatemporarily stored in the main memory 22 is then transferred to thestorage device 10 to be stored in the storage device 10. Accordingly, itmay take a relatively long amount of time to perform the reading/writingof the data using the NRD/NWR operations.

According to a direct load/store (DLS) operation in accordance withexemplary embodiments of the present inventive concept, the processor 21may directly access the storage device 10 without accessing the mainmemory 22 (e.g., without passing through the main memory 22). Forexample, the processor 21 may directly access at least one memory 120included in the controller 100 of the storage device 10.

Referring to the direct load operation, the processor 21 may load datafrom the at least one memory 120, and in the direct store operation, theprocessor 21 may temporarily store the data in the at least one memory120. The DLS operations may be performed by, for example, a devicedriver included in the host 20 and the controller 100 included in thestorage device 10.

The at least one memory 120 included in the storage device 10 may act asthe main memory 22 of the host 20, and accordingly, performancedegradation caused by a limitation in the capacity of the main memory 22may be reduced or prevented. Also, according to direct read/writeoperations performed using the DLS operations, the amount of time takento read/write data may be relatively short. As a result, the operatingspeed of the computing system 1 may be increased.

FIG. 2 is a block diagram of an example of a controller 100A included inthe storage device 10 of FIG. 1 according to an exemplary embodiment ofthe present inventive concept.

Referring to FIGS. 1 and 2, the controller 100A may include theprocessing unit 110, the at least one memory 120, and an interface unit130.

The interface unit 130 may interface with the host 20. For example, theinterface unit 130 may interface with the host 20 according to a firststandardized interface. The first standardized interface may be, forexample, a peripheral component interconnect express (PCIe). However,the first standardized interface not limited thereto. For example, thefirst standardized interface may be a universal serial bus (USB), smallcomputer system interface (SCSI), SCSI express (SCSIe), peripheralcomponent interconnect (PCI), advanced technology attachment (ATA),parallel ATA (PATA), serial ATA (SATA), serial attached SCSI (SAS),enhanced small device interface (ESDI), or integrated drive electronics(IDE).

The processing unit 110 may be connected to the interface unit 130 via afirst signal line SL1, and may perform the direct load operation or thedirect store operation between the host 20 and the controller 100A. Inaddition, the processing unit 110 may control overall operations of thecontroller 100A.

The at least one memory 120 may be connected to the interface unit 130via a second signal line SL2, and may temporarily store the data readfrom the storage medium 200 or the data transferred from the host 20. Inan exemplary embodiment, the at least one memory 120 may be directlyaccessed by the host 20. The at least one memory 120 is also connectedto the processing unit 110 to temporarily store data according tocontrol of the processing unit 110.

The first and second signal lines SL1 and SL2 may be referred to hereinas buses, metal lines, or data/signal paths. Each of the first andsecond signal lines SL1 and SL2 may communicate bi-directionally.

FIG. 3 is a block diagram of another example of the controller 100Bincluded in the storage device 10 of FIG. 1 according to an exemplaryembodiment of the present inventive concept.

Referring to FIGS. 1 and 3, the controller 100B may include theprocessing unit 110, the at least one memory 120, the first interfaceunit 130, and a second interface unit 140. Some of the componentsincluded in the controller 100B of the exemplary embodiment shown inFIG. 3 may be substantially the same as those of the controller 100Ashown in FIG. 2. For convenience of description, like components may bedenoted by like reference numerals, and may not be repeatedly described.Hereinafter, differences between the controller 100A shown in FIG. 2 andthe controller 100B shown in FIG. 3 will be described.

The first interface unit 130 may interface with the host 20. Forexample, the first interface unit 130 may interface with the host 20according to the first standardized interface (e.g., PCIe), as describedabove. However, as described above, the first standardized interface isnot limited thereto.

The second interface unit 140 may interface with the first interfaceunit 130. For example, the second interface unit 140 may interface withthe first interface unit 130 according to a second standardizedinterface. The second standardized interface may be, for example,Nonvolatile Memory Express (NVMe), Nonvolatile Memory Host ControllerInterface Specification (NVMHCI), or Small Computer System InterfaceExpress (SCSIe). However, the second standardized interface is notlimited thereto, and may be another type of interface.

The controller 100B may further include a first bus BUS1, a second busBUS2, and a third bus BUS3. The first bus BUS1 is connected to the firstinterface unit 130 and provides a communication path between the firstinterface unit 130 and the other components. The second bus BUS2 isconnected to the processing unit 110 and provides a communication pathbetween the processing unit 110 and the other components. The third busBUS3 is connected to the at least one memory 120 and provides acommunication path between the at least one memory 120 and the othercomponents.

The first through third buses BUS1, BUS2, and BUS3 may be implementedas, for example, a network interface card (NIC) or a bus matrix. Forexample, the bus matrix may be an advanced extended interface (AXI)interconnect of Advanced Microcontroller Bus Architecture 3 (AMBA3). TheAXI interconnect is a bus matrix structure having a plurality ofchannels, and may connect a plurality of bus masters and a plurality ofbus slaves to the plurality of channels at the same time using amultiplexer and a demultiplexer.

The first interface unit 130 may interface with the host 20, and thesecond interface unit 140 may interface with the first interface unit130. Accordingly, some of signals output from the second interface unit140 may be transferred to the processing unit 110 via the second busBUS2, and the other signals may be transferred to the at least onememory 120 via the third bus BUS3. As described above, if the signalsgenerated by the host 20 are transferred to the processing unit 110 andthe at least one memory 120 via the first interface unit 130 and thesecond interface unit 140, it may take a relatively long time totransfer the signals, and thus, the operating speed of the computingsystem 1 may be reduced.

According to an exemplary embodiment, the first signal line SL1 may bedirectly connected between the first bus BUS1 and the second bus BUS2,and the second signal line SL2 may be directly connected between thefirst bus BUS1 and the third bus BUS3. Accordingly, the signalsgenerated by the host 20 may be transferred from the first interfaceunit 130 to the processing unit 110 and the at least one memory 120without passing through the second interface unit 140. Accordingly, thetime taken to transfer the signals may be reduced and the operatingspeed of the computing system 1 may be improved. Therefore, a memoryaccessing speed between the host 20 and the storage device 10 may beincreased.

FIG. 4 is a block diagram of an example 110A of the processing unit 110included in the controller 100A of FIG. 2 according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 4, the processing unit 110A may include at least oneprocessor 112 and at least one tightly coupled memory (TCM) 114. Theprocessing unit 110A may further include firmware performing the directload/store operations described above.

In the exemplary embodiment shown in FIG. 4, four processors 112 andfour TCMs 114 are provided. However, exemplary embodiments of thepresent inventive concept are not limited thereto. For example,according to exemplary embodiments, the number of the at least oneprocessor 112 may be less than or greater than four, and the number ofthe at least one TCM 114 may be less than or greater than four.

The at least one processor 112 may perform the direct load operation orthe direct store operation described above. The at least one processor112 may be referred to herein as a central processing unit (CPU). In theexemplary embodiment shown in FIG. 4, since there is more than oneprocessor 112, the storage device 10 may perform multi-core processingand the operating speed of the storage device 10 may be increased.

The at least one TCM 114 may be disposed adjacent to the at least oneprocessor 112 and may be accessed by the at least one processor 112within a relatively short amount of time, for example, within one cycletime or a few cycle times. For example, each TCM 114 may be connected toa corresponding processor 112 via a dedicated channel and may act as adedicated memory of the corresponding processor 112. The at least oneTCM 114 may be disposed adjacent to the at least one processor 112.Herein, when the at least one TCM 114 is described as being disposedadjacent to the at least one processor 112, it is to be understood thatthe at least one TCM 114 is disposed directly next to or near the atleast one processor 112. For example, there may be no other componentsdisposed between the at least one TCM 114 and the at least one processor112. Further, the at least one TCM 114 and the at least one processor112 may be directly connected to each other via a dedicated connection.

In an exemplary embodiment, the at least one TCM 114 may store a datatransfer command that is transmitted between the controller 110A and thestorage medium 200. The data transfer command may include, for example,a flush command for transferring the data temporarily stored in the atleast one memory 120 to the storage medium 200, and a fill command fortransferring the data stored in the storage medium 200 to the at leastone memory 120. The flush command and the fill command are described infurther detail with reference to FIGS. 26 and 30.

FIG. 5 is a block diagram of another example of the processing unit 110Bincluded in the controller 100A of FIG. 2 according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 5, the processing unit 110B may include at least oneprocessor 112 and at least one TCM 114′. The at least one TCM 114′ mayinclude at least one special function register (SFR) 116. The processingunit 110B may further include firmware performing the direct load/storeoperations described above.

Some of the components included in the processing unit 110B of theexemplary embodiment shown in FIG. 5 may be substantially the same asthose of the processing unit 110A shown in FIG. 4. For convenience ofdescription, like components may be denoted by like reference numerals,and may not be repeatedly described.

The at least one SFR 116 may be used to perform the direct loadoperation or the direct store operation described above. For example,the at least one SFR 116 may store a doorbell representing initiation ofthe direct load operation or the direct store operation. The doorbell isdescribed in further detail below. The at least one SFR 116 will bedescribed in further detail with reference to FIG. 9.

FIG. 6 is a block diagram of another example of the processing unit 110Cincluded in the controller 100A of FIG. 2 according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 6, the processing unit 110C may include a firstprocessing unit 110 a and a second processing unit 110 b. The firstprocessing unit 110 a may include firmware performing the directload/store operations described above.

Some of the components included in the processing unit 110C shown inFIG. 6 may be substantially the same as those of the processing unit110A shown in FIG. 4. For convenience of description, like componentsmay be denoted by like reference numerals, and may not repeatedlydescribed.

The first processing unit 110 a (HCPU) may include at least one hostprocessor 112 a and at least one TCM 114. The first processing unit 110a may process various signals transmitted/received to/from the host 20.The second processing unit 110 b may include at least one processor 112b (FCPU) and at least one TCM 114. The second processing unit 110 b mayprocess various signals transmitted/received to/from the storage medium200.

FIG. 7 is a block diagram of an example of at least one memory 120Aincluded in the controller 100A of FIG. 2 according to an exemplaryembodiment of the present inventive concept.

Referring to FIGS. 1 and 7, the at least one memory 120A may include afirst memory 122 and a second memory 124. However, exemplary embodimentsof the present inventive concept are not limited thereto. For example,the at least one memory 120A may include three or more memories.

The first memory 122 may temporarily store raw data read from thestorage medium 200 or raw data received from the host 20. The raw datamay be stored in a page unit, and may be referred to as page data. In anexemplary embodiment, the first memory 122 may be a dynamic RAM (DRAM).For example, the first memory 122 may be a DRAM of 4 MB, andaccordingly, if a page has a size of 4 KB, the first memory 122 maystore 1024 pages. However, the sizes of the first memory 122 and thepage are not limited thereto.

The second memory 124 may temporarily store metadata of the raw datathat is temporarily stored in the first memory 122. The metadata may beinformation relating to the pages, and may be referred to as pageinformation. The page information may include, for example, DRAM relatedinformation, bitmap information, page to logical block address (LBA)mapping information, or partition information. In an exemplaryembodiment, the second memory 124 may be a static RAM (SRAM), forexample, an SRAM of 128 KB. However, the size of the second memory 124is not limited thereto.

FIG. 8 is a block diagram of another example of the at least one memory120B included in the controller 100A of FIG. 2 according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 8, the at least one memory 120B may include the firstmemory 122 and a second memory 124′. The second memory 124′ may includeat least one SFR 126. The at least one SFR 126 may be used to performthe direct load operation or the direct store operation described above.In an exemplary embodiment, the first memory 122 may include at leastone SFR.

FIG. 9 is a block diagram showing an example of the SFR 116 or 126included in the processing unit 110B of FIG. 5 or the at least onememory 120B of FIG. 8 according to an exemplary embodiment of thepresent inventive concept.

Referring to FIGS. 1 and 9, the at least one SFR 116 or 126 may include16 SFRs. However, exemplary embodiments are not limited thereto. A firstSFR may store, for example, the doorbell transferred from the host 20.The doorbell is a flag representing initiation of the direct loadoperation or the direct store information described above. A second SFRmay store an interrupt to be transferred to the host 20.

FIG. 10 is a block diagram of a computing system 1A according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 10, the computing system 1A may include a host 20A anda storage device 10A. The host 20A may include a processor 21 and aplurality of base address registers (BARs) 23. At least one of theplurality of BARs 23 may store a first address map AM1.

The plurality of BARs 23 are registers in which base address values arestored when executing a program. An absolute address may be found byadding a relative address value to the base address value. For example,the host 20A may include six BARs (e.g., BAR0 through BARS), and BAR4and BARS from among the six BARs may store addresses allocated withrespect to the memories included in the storage device 10A. However, thenumber of BARs is not limited thereto.

The storage device 10A may include a controller 100C and the storagemedium 200. The controller 100C may include a processing unit 110D and amemory 120A. The processing unit 110D may include at least one SFR 116.The memory 120A may include, for example, the DRAM 122 and the SRAM 124shown in FIG. 7.

FIG. 11 is a diagram showing an example of an address map AM1 of thememories included in the controller 100C of FIG. 10 according to anexemplary embodiment of the present inventive concept.

Referring to FIGS. 10 and 11, a first address map AM1 includes an SFRspace SP1, an SRAM space SP2, and a DRAM space SP3. The SFR space SP1,the SRAM space SP2, and the DRAM space SP3 may not overlap with eachother (e.g., the spaces may be allocated exclusively from each other).The processor 21 may directly access the SFR 116, the SRAM 124, and theDRAM 122 included in the storage device 10A with reference to the firstaddress map AM1.

The first address map AM1 is an address space that is allocated to thememories that the processor 21 may access. The first address map AM1 maybe stored in the host 20A, and the processor 21 may access the memorieswith reference to the first address map AM1. The first address map AM1shown in FIG. 11 only shows the address spaces that are allocated to thememories included in the storage device 10A from among the entireaddress maps included in the host 20A. The first address map AM1 may beconfigurable, and may be programmed if necessary.

FIG. 12 is a block diagram of a computing system 1B according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 12, the computing system 1B may include a host 20A anda storage device 10B. The host 20A may include the processor 21 and theplurality of BARs 23. At least one of the plurality of BARs 23 may storea second address map AM2.

The plurality of BARs 23 are registers in which base address values arestored when executing a program. An absolute address may be found byadding a relative address value to the base address value. For example,the host 20A may include six BARs 23 (e.g., BAR0 through BARS), and BARSfrom among the six BARs 23 may store the address spaces allocated to thememories included in the storage device 10B.

The storage device 10B may include a controller 100D and the storagemedium 200. The controller 100D may include a processing unit 110E andthe memory 120A. The processing unit 110E may include at least oneprocessor 112, at least one TCM 114, and at least one SFR 116. Thememory 120A may include the DRAM 122 and the SRAM 124.

FIG. 13 is a diagram showing an example of an address map AM2 of thememories included in the controller 100D of FIG. 12 according to anexemplary embodiment of the present inventive concept.

Referring to FIGS. 12 and 13, the second address map AM2 may include anSFR space SP1, an SRAM space SP2, a DRAM space SP3, and a TCM space SP4.Thus, when compared with the first address map AM1 shown in FIG. 11, thesecond address map AM2 may further include the TCM space SP4. Forconvenience of description, the above description relating to FIG. 11that applies to FIG. 13 may be omitted herein.

The SFR space SP1, the SRAM space SP2, the DRAM space SP3, and the TCMspace SP4 may not overlap with each other. For example, these spaces maybe allocated exclusively from each other. The processor 21 may directlyaccess the SFR 116, the SRAM 124, the DRAM 122, and the TCM 114 includedin the storage device 10B with reference to the second address map AM2.

The TCM space SP4 may include a first TCM space SP4 a, a second TCMspace SP4 b, and a third TCM space SP4 c. The TCM space SP4 may furtherinclude TCM spaces allocated respectively to other TCMs. Thus, thenumber of sub-spaces included in the TCM space SP4 is not limited tothree.

The first TCM space SP4 a is an address space allocated to a first TCM(TCM0) that is connected to a first processor CPU0 via a dedicatedchannel, the second TCM space SP4 b is an address space allocated to thesecond TCM (TCM1) that is connected to a second processor CPU1 via adedicated channel, and a third TCM space SP4 c is an address spaceallocated to a third TCM (TCM2) that is connected to a third processorCPU2 via a dedicated channel.

As described above, the TCM space SP4 may be divided into a plurality ofsub-spaces (e.g., SP4 a, SP4 b, and SP4 c) according to the number ofthe plurality of TCMs included in the processing unit 110E. Theplurality of sub-spaces (e.g., SP4 a, SP4 b, and SP4 c) may not overlapwith each other and may be allocated exclusively from each other.

FIG. 14 is a block diagram of a computing system 1C according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 14, the computing system 1C may include the host 20Aand a storage device 10C. The host 20A may include the processor 21 andthe plurality of BARs 23. At least one of the plurality of BARs 23 maystore an address map AM3.

The plurality of BARs 23 are registers in which base address values arestored when executing a program. An absolute address may be found byadding a relative address value to the base address value. For example,the host 20A may include six BARs 23 (e.g., BAR0 through BARS), and BARSfrom among the six BARs 23 may store the address spaces allocated to thememories included in the storage device 10C.

The storage device 10C may include a controller 100E and the storagemedium 200. The controller 100E may include the processing unit 110B andthe memory 120A. The processing unit 110B may include at least oneprocessor 112 and at least one TCM 114′. The at least one TCM 114′ mayinclude at least one SFR 116. The memory 120A may include the DRAM 122and the SRAM 124.

FIG. 15 is a diagram showing an example of an address map AM3 of thememories included in the controller 100E of FIG. 14 according to anexemplary embodiment of the present inventive concept.

Referring to FIGS. 14 and 15, the third address map AM3 may include theSRAM space SP2, the DRAM space SP3, and the TCM space SP4. Forconvenience of description, the above descriptions with reference toFIGS. 10 through 13 may be applied to FIG. 15, and thus, may be omittedherein.

The SRAM space SP2, the DRAM space SP3, and the TCM space SP4 may notoverlap with each other and may be allocated exclusively from eachother. The processor 21 may directly access the SRAM 124, the DRAM 122,the TCM 114′, and the SFR 116 included in the storage device 10C withreference to the third address map AM3.

The TCM space SP4 may be divided into a plurality of sub-spacesincluding, for example, the first TCM space SP4 a, the second TCM spaceSP4 b, and the third TCM space SP4 c. At least one of the plurality ofsub-spaces, for example, the first TCM space SP4 a, may be partiallyallocated as an SFR space. The number of sub-spaces of the TCM space SP4is not limited thereto.

FIG. 16 is a diagram of an address map used in the computing system 1 ofFIG. 1 according to an exemplary embodiment of the present inventiveconcept.

Referring to FIG. 16, a part of the address map relating to the memoriesthat the host 20 may access may be allocated for performing the directload/store operations described above. The allocated space for thedirect load/store operations may be stored in the host 20. For example,the allocated space for the direct load/store operations may be storedin BAR4 and BARS.

Context of the host 20 may have, for example, logical block addressing(LBA) information. The context of the host 20 may be mapped to the TCMspace or the SRAM space of the controller 100. The data may be mappedwith the DRAM space of the controller 100. The data mapped with the DRAMspace may be mapped with the storage medium 200 using a page tablestored in the TCM space or the SRAM space.

FIG. 17 is a diagram of an example of the at least one memory 120included in the controller 100A of FIG. 2 according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 17, the at least one memory 120 may be, for example, aDRAM that may be classified as a data area DA including a plurality ofdata pages and an information area IA including info pages representinginformation about the data pages.

A size of each of the data pages may be, for example, 4 KB, and the DRAMmay include, for example, 1024 pages. Accordingly, the data area DA mayhave a capacity of about 4 MB. The information area IA may be about 14KB. The information area IA may include, for example, a tablerepresenting DRAM information, bitmap information, page map information,and partition layout information. The size of the data pages, the dataarea DA and the information area IA are not limited thereto.

FIG. 18 is a block diagram of an example of an interface unit 130Aincluded in the controller 100A of FIG. 2 according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 18, the interface unit 130A may include a signaltransfer unit 132 and an address conversion unit 134. The interface unit130A may further include a buffer memory (e.g., an SRAM).

The signal transfer unit 132 may transmit/receive a signal to/from thehost 20. In an exemplary embodiment, the interface unit 130A mayinterface with the host 20 according to PCIe, and the signal transferunit 132 may receive a signal from the host 20 via a PCIe bus and mayprovide the signal with electrical and mechanical interfacing. However,the interface type is not limited to PCIe, and may include otherstandardized interfaces, as described above. The signal transfer unit132 may transfer a signal generated by the controller 100A to the host20 via the PCIe bus, and may provide the signal that is to betransferred via the electrical and mechanical interfacing.

The signal transfer unit 132 may be formed of, for example, a physicallayer (PHY), and may be referred to as a PHY core. The signal transferunit 132 may be referred to as a port.

The address conversion unit 134 may perform address conversion between ahost address space and a controller address space. For example, theaddress conversion unit 134 may convert an external address ADDR_EX ofthe signal received from the host 20 to an internal address ADDR_IN thatis suitable for internal communication within the controller 100A. Theaddress conversion unit 134 may convert the internal address ADDR_IN tothe external address ADDR_EX. Operations of the address conversion unit134 will be described with reference to FIG. 20.

FIG. 19 is a block diagram of another example of the interface unit 130Bincluded in the controller 100A of FIG. 2 according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 19, the interface unit 130B may include a plurality ofsignal transfer units including, for example, a first signal transferunit 132 and a second signal transfer unit 136, and a plurality ofaddress conversion units including, for example, a first addressconversion unit 134 and a second address conversion unit 138. However,exemplary embodiments are not limited thereto. For example, theinterface unit 130B may include three or more signal transfer units andthree or more address conversion units. The interface unit 130B mayfurther include a buffer memory (e.g., an SRAM).

The first and second signal transfer units 132 and 136 maytransmit/receive signals to/from the host 20, respectively. The firstand second signal transfer units 132 and 136 may be implemented asseparate ports to process the signals in parallel. As a result, a highspeed access operation between the host 20 and the storage device 10 maybe implemented.

FIG. 20 is a diagram of an operation of the address conversion unit 134included in the interface unit 130A of FIG. 18 according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 20, the address conversion unit 134 may performaddress conversion between the host address space and the controlleraddress space. The address of the host address space is the externaladdress ADDR_EX, and the address of the controller address space is theinternal address ADDR_IN.

The external address ADDR_EX is a standard interface between the host 20and the storage device 10, for example, an address according to the PCIestandard, and may be referred to as a host address. However, thestandard interface is not limited to PCIe. The external address ADDR_EXmay be, for example, 64 bits, however the size of the external addressADDR_EX is not limited thereto. The internal address ADDR_IN is suitablefor the internal communication in the controller 100A, and may bereferred to as a controller address. The internal address ADDR_IN maybe, for example, 32 bits, however the size of the internal addressADDR_IN is not limited thereto.

The address conversion unit 134 may convert the external address ADDR_EXof the first TCM (TCM0), 0x0000_0000, to the internal address ADDR_IN0x4080_0000. Further, the address conversion unit 134 may convert theexternal address ADDR_EX of the DRAM, 0x000e_0000, to the internaladdress ADDR_IN 0x4780_0000.

FIG. 21 is a block diagram of an example of the second interface unit140′ included in the controller 100B of FIG. 3 according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 21, the second interface unit 140′ may interface withthe first interface unit 130. The second interface unit 140′ may includea plurality of sub-interface units 142 and 144. Although the secondinterface unit 140′ shown in FIG. 21 includes first and secondsub-interface units 142 and 144, exemplary embodiments are not limitedthereto. For example, the second interface unit 140′ may include threeor more sub-interface units.

The second interface unit 140′ may selectively activate one of theplurality of sub-interface units 142 and 144 to interface with the firstinterface unit 130. The second interface unit 140′ may further include aplurality of multiplexers and a plurality of demultiplexers, and mayselectively activate one of the plurality of sub-interface units 142 and144 according to a selection signal applied from an external source.

In an exemplary embodiment, the first sub-interface unit 142 mayinterface with the first interface unit 130 according to SCSIe, and thesecond sub-interface unit 144 may interface with the first interfaceunit 130 according to NVMe. However, exemplary embodiments are notlimited thereto. For example, the first and second sub-interface units142 and 144 may interface with the first interface unit 130 according toother standardized interfaces.

The second interface unit 140′ may further include a buffer memory(e.g., an SRAM), and the first and second sub-interface units 142 and144 may share the buffer memory. The second interface unit 140′ mayfurther include a bus for communication between the first and secondsub-interface units 142 and 144 and the buffer memory.

FIG. 22 is a flowchart illustrating a method of operating a storagedevice according to an exemplary embodiment of the present inventiveconcept.

Referring to FIG. 22, a method of operating a storage device accordingto an exemplary embodiment is a method of directly accessing thememories included in the storage device by the host. The methoddescribed with reference to FIG. 22 may be implemented according to theexemplary embodiments described above with reference to FIGS. 1 through21. Hereinafter, the method of operating the storage device according toan exemplary embodiment will be described with reference to FIGS. 1, 2and 22.

In operation S120, a storage device may receive a direct load command ora direct store command from a host. For example, the storage device 10may receive the direct load command or the direct store command from thehost 20. The direct load command causes a direct load operation to beperformed, and the direct store command causes a direct store operationto be performed. For example, the direct load command instructs thestorage device 10 to perform a direct load operation, and the directstore command instructs the storage device 10 to perform a direct storeoperation.

In operation S140, a status of the memory is determined. For example,the processing unit 110 may determine a status of the at least onememory 120. For example, the processing unit 110 determines whether theat least one memory 120 is in a status suitable for executing the directload operation or the direct store operation.

In operation S160, the direct load operation or the direct storeoperation is performed. For example, data that is temporarily stored inthe at least one memory 120 is loaded to the host 20 or data receivedfrom the host 20 is temporarily stored in the at least one memory 120based on a determination result to perform the direct load operation orthe direct store operation between the host 20 and the at least onememory 120.

FIG. 23 is a flowchart illustrating a method of operating a storagedevice according to an exemplary embodiment of the present inventiveconcept.

Referring to FIG. 23, the method of operating the storage device 10according to an exemplary embodiment is an initialization method forperforming the direct load/store operations, and may be performed beforeoperation S120 shown in FIG. 22. The initialization method of FIG. 23may be performed to allow the host to recognize a hardware configurationof the storage device to perform the direct load/store operations. Themethod described with reference to FIG. 23 may be implemented accordingto the exemplary embodiments described above with reference to FIGS. 1through 22. Hereinafter, the method of operating the storage deviceaccording to an exemplary embodiment will be described with reference toFIGS. 1, 2, 22 and 23.

In operation S110, device information is stored in a memory. The deviceinformation may include, for example, DRAM information, DRAM capacity,DRAM version, a page size, the number of information pages, the numberof data pages, an LBA size, start LBA, end LBA, bitmap offset, page maptable offset, partition layout offset, and padding.

FIG. 24 is a schematic diagram showing an example of operation S110 ofFIG. 23 according to an exemplary embodiment of the present inventiveconcept.

Referring to FIG. 24, device information may be loaded from the storagemedium 200 to the memory 120 according to an operation initiating signal(e.g., a power-on signal) or an initialization command. The deviceinformation may be stored in a certain region of the storage medium 200that is known to a host driver or firmware in advance or ispre-compromised. The certain region storing the device information inthe storage medium 200 may be, for example, a base address or an addressdivided by a certain offset.

The device information stored in the storage medium 200 may betransferred or copied to the information area IA (see FIG. 17) in thememory 120. In an exemplary embodiment, the device information stored inthe storage medium 200 may be transferred or copied to the DRAM 122 orthe SRAM 124 of FIG. 7 or FIG. 8. In an exemplary embodiment, the deviceinformation stored in the storage medium 200 may be transferred orcopied to the TCM 114 of FIGS. 4 through 6. In an exemplary embodiment,the device information stored in the storage medium 200 may betransferred or copied to the SFR 116 of FIG. 5 or the SFR 126 of FIG. 8.

The information area IA in the memory 120 is allocated as an exclusivearea in the address map, and may be a pre-compromised area with the hostdriver or the firmware. The device information copied from the storagemedium 200 may have a default value, which may be changed by an explicitcommand generated by the host 20.

FIG. 25 is a schematic diagram of another example of operation S110shown in FIG. 23 according to an exemplary embodiment of the presentinventive concept.

Referring to FIG. 25, in an exemplary embodiment of the presentinventive concept, the host 20, for example, using an applicationprotocol interface (API), may directly write device information in acertain address of the memory 120. The certain address of the memory 120may be pre-compromised with the host driver or the firmware, and maycorrespond to the information area IA (see FIG. 17) in the memory 120.In an exemplary embodiment, the API may directly write the deviceinformation in the DRAM 122 or the SRAM 124 of FIG. 7 or FIG. 8. In anexemplary embodiment, the API may directly write the device informationin the TCM 114/114′ of FIGS. 4 through 6. In an exemplary embodiment,the API may directly write the device information in the SFR 116 of FIG.5 or the SFR 126 of FIG. 8.

Referring back to FIG. 23, in operation S115, the device information istransferred to the host. For example, the controller 100 may transferthe device information to the host 20. As a result, the host 20 mayrecognize the hardware configuration of the storage device 10, and thus,may appropriately instruct the direct load/store operations to beperformed.

FIG. 26 is a flowchart illustrating a method of operating a storagedevice according to an exemplary embodiment of the present inventiveconcept.

FIG. 26 illustrates operation S140 and operation S160 of FIG. 22 infurther detail. The method described with reference to FIG. 26 may beimplemented according to the exemplary embodiments described above withreference to FIGS. 1 through 25. Hereinafter, the method of operatingthe storage device according to an exemplary embodiment will bedescribed with reference to FIGS. 1, 2 and 26.

In operation S1420, it is determined whether a received command is adirect load command. For example, the processing unit 110 may determinewhether the command received from the host 20 is a direct load command.If the command is a direct load command, operation S1440 is performed.If the command is not a direct load command (e.g., if the command is adirect store command), operation S1460 is performed.

In operation S1440, it is determined whether there is first data in thememory. The first data is data corresponding to the direct load commandand data that is to be loaded by the host 20. For example, theprocessing unit 110 or a memory manager may determine whether the firstdata is in the memory 120. If the first data is not in the memory 120,operation S1620 is performed. If the first data is in the memory 120,operation S1640 is performed.

In operation S1620, the first data is received from the storage mediumto the memory 120. The above operations may be referred to as a filloperation. For example, the storage medium 200 may transfer or copy thefirst data to the memory 120, and then, the memory 120 may temporarilystore the first data.

In operation S1640, the first data is loaded to the host. For example,the first data temporarily stored in the memory 120 may be loaded to thehost 20. Thus, the execution of the direct load operation may becompleted.

In operation S1460, it is determined whether there is a clearance spacein the memory. The clearance space may store second data correspondingto the direct store command, the second data being the data that thehost 20 is to store. For example, the processing unit 110 or the memorymanager may determine whether the clearance space is in the memory 120.If the clearance space is not in the memory 120, operation S1660 isperformed. If the clearance space is in the memory 120, operation S1680is performed.

In operation S1660, the data temporarily stored in the memory istransferred to the storage medium. The above operations may be referredto as a flush operation. For example, the memory 120 may transfer thetemporarily stored data to the storage medium 200, and the memory 120may then ensure a clearance space.

In operation S1680, the second data may be stored in the memory. Forexample, the host 20 may store the second data in the memory 120, andexecution of the direct store operation may be completed.

FIG. 27 is a schematic diagram of a direct load operation according toan exemplary embodiment of the present inventive concept.

Referring to FIG. 27, the direct load operation of an exemplaryembodiment corresponds to executing the direct load command receivedfrom the host in a case in which there is available data in the memoryof the storage device. Hereinafter, the direct load operation accordingto an exemplary embodiment will be described with reference to FIGS. 1and 27.

First, the host 20 transmits a direct load command DL_CMD to thecontroller 100. The memory 120 of the controller 100 stores first dataDATA1 corresponding to the direct load command DL_CMD (e.g., availabledata). Next, the controller 100 transfers the first data DATA1 to thehost 20, and execution of the direct load operation may be completed.

FIG. 28 is a schematic diagram of a direct load operation according toan exemplary embodiment of the present inventive concept.

Referring to FIG. 28, the direct load operation according to anexemplary embodiment corresponds to executing the direct load commandreceived from the host in a case in which there is no available data inthe memory of the storage device. Hereinafter, the direct load operationaccording to an exemplary embodiment will be described with reference toFIGS. 1 and 28.

First, the host 20 transmits a direct load command DL_CMD to thecontroller 100. The memory 120 of the controller 100 does not store thefirst data DATA1 corresponding to the direct load command DL_CMD (e.g.,available data).

In addition, the controller 100 transmits a fill command FILL_CMD to thestorage medium 200. The fill command FILL_CMD may be generated by thehost 20. The storage medium 200 includes the first data DATA1corresponding to the direct load command DL_CMD (e.g., the availabledata).

In addition, the storage medium 200 transfers or copies the first dataDATA1 to the controller 100. As a result, the memory 120 may temporarilystore the first data DATA1. Next, the controller 100 transmits the firstdata DATA1 to the host 20, and execution of the direct load operationmay be completed.

FIG. 29 is a diagram of an example of the fill operation shown in FIG.28 according to an exemplary embodiment of the present inventiveconcept.

Referring to FIG. 29, the fill operation of an exemplary embodimentcorresponds to executing a fill command received from the host if thereis no available data in the memory of the storage device. Hereinafter,the fill operation of an exemplary embodiment will be described withreference to FIGS. 1, 28 and 29.

First, the host 20 sets bits in a fill operation bitmap fill_op_bitmap.Next, the controller 100 notifies the firmware in the processing unit110 of the arrival of the fill command Fill_CMD.

Then, the firmware reads the fill operation bitmap fill_op_bitmap toread a page map table page_map_table. In addition, the firmware readspages corresponding to the bits that are set in the fill operationbitmap fill_op_bitmap or the fill operation page fields. Duringoperation of the firmware, the host 20 may selectively perform pollingof the fill operation bitmap fill_op_bitmap in order to check whetherthe fill operation with respect to an arbitrary page is finished. Then,when the fill operations with respect to certain pages are finished, thefirmware clears the bits in the fill operation bitmap fill_op_bitmap,and repeatedly performs the above operations until all bits in the filloperation bitmap fill_op_bitmap are cleared.

Next, the firmware notifies the controller 100 of the completion of thefill operation. The controller 100 triggers an interrupt in the host 20,and the host 20 processes the interrupt.

FIG. 30 is a diagram of an example of an operation of setting the filloperation bitmap fill_op_bitmap shown in FIG. 29 according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 30, the memory, for example, the DRAM, may include1024 pages (page 0000 through page 1023), and a size of each page may be4 KB. For example, numbers of target pages in which the fill operationsare performed may be {0032, 0035, 0063} and {0099, 0126}. The host 20may generate a fill operation bitmap fill_op_bitmap in which bitscorresponding to the numbers of the target pages are set as ‘1’, and mayperform the fill operation by using the fill operation bitmapfill_op_bitmap. It is to be understood that FIG. 30 is exemplary, andexemplary embodiments are not limited thereto.

FIG. 31 is a schematic diagram of a direct store operation according toan exemplary embodiment of the present inventive concept.

Referring to FIG. 31, the direct store operation according to anexemplary embodiment corresponds to performing a direct store commandreceived from the host if there is an available space in the memory ofthe storage device. Hereinafter, the direct store operation according toan exemplary embodiment will be described with reference to FIGS. 1 and31.

First, the host 20 transmits a direct store command DS_CMD to thecontroller 100. Here, the memory 120 in the controller 100 has anavailable space for storing data. The available space may store seconddata DATA2 corresponding to the direct store command DS_CMD. The seconddata DATA2 is the data to be stored at the host 20. Next, the host 20directly stores the second data DATA2 in the memory 120 of thecontroller 100, and accordingly, the execution of the direct storeoperation may be completed.

FIG. 32 is a schematic diagram of a direct store operation according toan exemplary embodiment of the present inventive concept.

Referring to FIG. 32, the direct store operation according to anexemplary embodiment corresponds to performing the direct store commandreceived from the host if there is no available space in the memory ofthe storage device. Hereinafter, the direct store operation according toan exemplary embodiment will be described with reference to FIGS. 1 and32.

First, the host 20 transmits the direct store command DS_CMD to thecontroller 100. Here, the memory 120 in the controller 100 has noavailable space (e.g., the memory 120 is filled with other data).

Next, the controller 100 transmits a flush command FLUSH_CMD to thestorage medium 200, and transfers the data filled in the memory 120 tothe storage medium 200. Here, the flush command FLUSH_CMD may begenerated by the host 20. As such, the memory 120 may ensure anavailable space.

In addition, the host 20 directly writes the second data DATA2 in thememory 120 of the controller 100. Accordingly, execution of the directstore operation may be completed.

FIG. 33 is a diagram of an example of the flush operation shown in FIG.32 according to an exemplary embodiment of the present inventiveconcept.

Referring to FIG. 33, the flush operation according to an exemplaryembodiment corresponds to executing the flush command received from thehost if there is no available space in the memory of the storage device.Hereinafter, the flush operation according to an exemplary embodimentwill be described with reference to FIGS. 1, 32 and 33.

First, the host 20 fills pages of the memory 120, for example, DRAM,with data, and sets bits in a flush operation bitmap flush_op_bitmap.The host 20 further sets the bits in the SFR, and may initiate theoperation by setting the doorbell as ‘1’. Then, the controller 100notifies the firmware in the processing unit 110 of the arrival of theflush command FLUSH_CMD.

The firmware reads the flush operation bitmap flush_op_bitmap and readsthe page_map_table. In addition, the firmware flushes the pagescorresponding to the bits that are set in the flush operation bitmapflush_op_bitmap. During operation of the firmware, the host 20 mayselectively perform a polling operation of the flush operation bitmapflush_op_bitmap to check whether the flush operation with respect to anarbitrary page is finished. Next, the firmware clears the bits in theflush operation bitmap flush_op_bitmap when the flush operations withrespect to certain pages are finished.

In addition, the firmware notifies the controller 100 of the completionof the flush operation. Next, the controller 100 triggers an interruptin the host 20, and the host 20 processes the interrupt.

FIG. 34 is a diagram showing an example of an operation of setting anindex in pages to be flushed included in FIG. 33 according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 34, the memory 120, for example, the DRAM, may have1024 pages (page 0000 through page 1023), and a size of each page may be4 KB. For example, numbers of target pages in which the flush operationsare performed may be {0032, 0035, 0063} and {0099, 0126}. The host 20may separately manage the pages corresponding to the numbers of thetarget pages as page index, and may perform the flush operation usingthe page index. When the flush operation is finished, the page is resetas 0000, and accordingly, the memory 120 may have clearance space andthe host 20 may directly store the data in the memory 120. It is to beunderstood that FIG. 34 is exemplary, and exemplary embodiments are notlimited thereto.

FIG. 35 is a block diagram of a memory system 1000 according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 35, the memory system 1000 may include a controller1100 and a nonvolatile memory device 1200. The controller 1100 may bethe controller 100 of FIG. 1, and the nonvolatile memory device 1200 mayinclude the storage medium 200 of FIG. 1.

The controller 1100 is configured to access the nonvolatile memorydevice 1200 in response to a request from a host. For example, thecontroller 1100 is configured to control reading, writing, erasing, andbackground operations of the nonvolatile memory device 1200. Thecontroller 1100 is further configured to provide an interface betweenthe nonvolatile memory device 1200 and the host, and may be configuredto drive firmware for controlling the nonvolatile memory device 1200.

The nonvolatile memory device 1200 or the memory system 1000 accordingto exemplary embodiments of the present inventive concept may be mountedusing various types of packages. For example, the nonvolatile memorydevice 1200 or the memory system 1000 may be mounted by using a packageon package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), aplastic leaded chip carrier (PLCC), a plastic dual in-line package(PDIP), a die in waffle pack, a die in wafer form, a chip on board(COB), a ceramic dual in-line package (CERDIP), a plastic metric quadflat pack (MQFP), a thin quad flat pack (TQFP), a small outlineintegrated chip (SOIC), a shrink small outline package (SSOP), a thinsmall outline package (TSOP), a thin quad flat pack (TQFP), a system inpackage (SIP), a multichip package (MCP), a wafer-level fabricatedpackage (WFP), or a wafer-level processed stack package (WSP).

FIG. 36 is a block diagram of a storage system 2000 according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 36, the storage system 2000 may include a controller2100 and a nonvolatile memory device 2200. The controller 2100 may bethe controller 100 of FIG. 1, and the nonvolatile memory device 2200 mayinclude the storage medium 200 of FIG. 1.

The nonvolatile memory device 2200 includes a plurality of nonvolatilememory chips. The plurality of nonvolatile memory chips may be dividedinto a plurality of groups. Each of the groups of the plurality ofnonvolatile memory chips may be configured to communicate with thecontroller 2100 via common channels. For example, the plurality ofnonvolatile memory chips may communicate with the controller 2100 viafirst through k-th channels CH1 through CHk.

In FIG. 36, the plurality of nonvolatile memory chips are connected toone channel. However, exemplary embodiments are not limited thereto. Forexample, the memory system 2000 may be configured such that onenonvolatile memory chip is connected to one channel.

FIG. 37 is a block diagram of a user device 3000 according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 37, the user device 3000 may include a memory system3100, a central processing unit 3200, a RAM 3300, a user interface 3400,and a power source 3500. The memory system 3100 is electricallyconnected to the central processing unit 3200, the RAM 3300, the userinterface 3400, and the power source 3500 via a system bus. Dataprovided through the user interface 3400 or processed by the centralprocessing unit 3200 may be stored in the memory system 3100.

The memory system 3100 may include a controller 3110 and a nonvolatilememory device 3120. The controller 3110 may be the controller 100 ofFIG. 1, and the nonvolatile memory device 3120 may be the storage medium200 of FIG. 1. The nonvolatile memory device 3120 may include aplurality of nonvolatile memory chips. In FIG. 37, the nonvolatilememory device 3120 is connected to the system bus via the controller3110. However, exemplary embodiments are not limited thereto. Forexample, the nonvolatile memory device 3120 may be directly connected tothe system bus.

FIG. 38 is a block diagram of a storage server 4000 according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 38, the storage server 4000 may include a server 4100and a plurality of storage devices including, for example, a firststorage device 4200 and a second storage device 4300. The storage server4000 may further include a RAID controller 4400.

The first storage device 4200 may include a controller 4210 and astorage medium 4220. The second storage device 4300 may include acontroller 4310 and a storage medium 4320. The controllers 4210 and 4310may be the controller 100 of FIG. 1, and the storage mediums 4220 and4320 may be the storage medium 200 of FIG. 1.

FIG. 39 is a block diagram of a storage server 5000 according to anexemplary embodiment of the present inventive concept. Referring to FIG.39, the storage server 5000 may include a server 5100, a controller5200, and a plurality of storage devices including, for example, a firststorage device 5300 and a second storage device 5400. The storage server5000 may further include a RAID controller 5500.

The first storage device 5300 may include a controller 5310 and astorage medium 5320. The second storage device 5400 may include acontroller 5410 and a storage medium 5420. The first and secondcontrollers 5310 and 5410 may be the controller 100 of FIG. 1, and thestorage mediums 5320 and 5420 may be the storage medium 200 of FIG. 1.

FIG. 40 is a schematic diagram of a system 6000 to which the storagedevice according to exemplary embodiments of the present inventiveconcept may be applied.

Referring to FIG. 40, a semiconductor device including the storagedevice according to the exemplary embodiments of the present inventiveconcept described herein may be applied to a storage device 6100. Thesystem 6000 may include a host 6200 and the storage device 6100communicating with the host 6200 via a wired or wireless connection. Thestorage device 6100 may be one of the storage devices according to theexemplary embodiments of the present inventive concept described above(e.g., storage device 10 of FIG. 1).

FIG. 41 is a schematic diagram of a system 7000 to which a storagedevice according to exemplary embodiments of the present inventiveconcept may be applied.

Referring to FIG. 41, a semiconductor device including the storagedevice according to the exemplary embodiments of the present inventiveconcept described herein may be applied to storage servers 7100 and7200. The system 7000 may include a plurality of hosts 7300 and 7400 anda plurality of storage servers 7100 and 7200. The storage servers 7100and 7200 may include one of the storage device according to theexemplary embodiments of the present inventive concept described above(e.g., storage device 10 of FIG. 1).

FIG. 42 is a schematic diagram of a system 8000 to which the storagedevice according to exemplary embodiments of the present inventiveconcept may be applied.

Referring to FIG. 42, a semiconductor device including the storagedevice according to the exemplary embodiments of the present inventiveconcept described herein may be applied to a server 8100 utilized forimplementing email.

While the present inventive concept has been particularly shown anddescribed with reference to the exemplary embodiments thereof, it willbe understood by those of ordinary skill in the art that various changesin form and detail may be made therein without departing from the spiritand scope of the present inventive concept as defined by the followingclaims.

What is claimed is:
 1. A method of operating a storage device includinga controller and a storage medium, the method comprising: receiving afirst request from a host; determining whether the first requestincludes a direct load request or a direct store request; and performinga direct load operation in response to the direct load request byloading a first data stored in a buffer memory to the host or performingthe direct store operation in response to the direct store request bystoring a second data received from the host in the buffer memory,wherein the buffer memory is included in the controller, and isconfigured to be directly accessible by the host.
 2. The method of claim1, wherein the direct load operation further comprises determining,while performing the direct load request, whether the first data is inthe buffer memory, and if determined that the first data is in thebuffer memory, loading the first data to the host.
 3. The method ofclaim 2, wherein, if determined that the first data is not in the buffermemory, performing a fill operation in which transmitting the first datastored in the storage medium to the buffer memory, and then loading thefirst data to the host.
 4. The method of claim 1, wherein the directstore operation further comprises determining, while performing thedirect store command, whether the buffer memory has enough space foraccommodating the second data, and if determined that the buffer memoryhas enough space, storing the second data in the buffer memory.
 5. Themethod of claim 4, wherein, if determined that the buffer memory has notenough space, performing a flush operation in which transmitting a thirddata included in the buffer memory to the storage medium to secureenough space for storing the second data, and then storing the seconddata in the buffer memory.
 6. The method of claim 1, further comprisingstoring device information relating to the storage device in the buffermemory before receiving the first request, wherein the deviceinformation indicates a hardware configuration of the storage device tothe host and the host utilizes the hardware configuration to issue thefirst request.
 7. The method of claim 6, wherein storing the deviceinformation in the buffer memory comprises receiving the deviceinformation from the storage medium in response to an operationinitiation signal or an initialization command, and storing the deviceinformation in the buffer memory.
 8. The method of claim 1, wherein thecontroller comprises a processor, and a tightly coupled memory (TCM)disposed adjacent to the processor and accessible by the processor,wherein the buffer memory and the TCM are mapped to address spaces thatare exclusive from each other in an address map.
 9. The method of claim8, wherein the processor is configured to process the direct loadoperation and the direct store operation, and the TCM is configured tobe directly accessible by the processor.
 10. The method of claim 9,wherein the TCM is further configured to temporarily store a datatransfer command for communicating data between the controller and thestorage medium.
 11. The method of claim 10, wherein the data transfercommand includes a flush command for transmitting a third datatemporarily stored in the buffer memory to the storage medium, and afill command for transmitting the first data stored in the storagemedium to the buffer memory.
 12. The method of claim 10, wherein the TCMincludes at least one special function register (SFR) configured toperform the direct load operation and the direct store operation. 13.The method of claim 1, wherein the buffer memory comprises a firstportion configured to temporarily store raw data read from the storagemedium or raw data received from the host, and a second portionconfigured to temporarily store metadata corresponding to the raw data.14. The method of claim 1, wherein the buffer memory comprises at leastone DRAM device and/or at least one SRAM device.
 15. A method ofoperating a storage device including a controller and a storage medium,the method comprising: receiving a first request from a host;determining whether the first command includes a normal write/readrequest or a direct load/store request; and performing a normalwrite/read operation in response to the normal write/read request orperforming a direct load/store operation in response to the directload/store request, wherein the direct load/store operation comprises:determining whether the direct load/store request is a direct loadrequest or a direct store request; and performing a direct loadoperation upon receiving the direct load request by loading a first datastored in a buffer memory to the host or performing the direct storeoperation upon receiving the direct store request by storing a seconddata received from the host in the buffer memory, wherein the buffermemory is included in the controller, and is configured to be directlyaccessible by the host.
 16. The method of claim 15, wherein, duringnormal write/read operation, a data to be written to or read from thestorage medium is temporarily stored in a main memory which isconfigured to be accessible by the host, and the main memory is locatedoutside the storage device.
 17. The method of claim 15, wherein thedirect load operation further comprises determining, while performingthe direct load request, whether the first data is in the buffer memory,and if determined that the first data is in the buffer memory, loadingthe first data to the host.
 18. The method of claim 17, wherein, ifdetermined that the first data is not in the buffer memory, performing afill operation in which transmitting the first data stored in thestorage medium to the buffer memory, and then loading the first data tothe host.
 19. The method of claim 15, wherein the direct store operationfurther comprises determining, while performing the direct storecommand, whether the buffer memory has enough space for accommodatingthe second data, and if determined that the buffer memory has enoughspace, storing the second data in the buffer memory.
 20. The method ofclaim 19, wherein, if determined that the buffer memory has not enoughspace, performing a flush operation in which transmitting a third dataincluded in the buffer memory to the storage medium to secure enoughspace for storing the second data, and then storing the second data inthe buffer memory.